Reset; Overview; Reset Sequence - Hitachi H8S/2646 Hardware Manual

4.2

Reset

4.2.1

Overview

A reset has the highest exception priority.
When the RES pin goes low, all current operations are stopped, and this LSI enters reset state. A
reset initializes the internal state of the CPU and the registers of on-chip supporting modules.
Immediately after a reset, interrupt control mode 0 is set.
When the RES pin goes from low to high, reset exception handling starts.
The H8S/2646 Series can also be reset by overflow of the watchdog timer. For details see section
12, Watchdog Timer.
4.2.2

Reset Sequence

This LSI enters reset state when the RES pin goes low.
To ensure that this LSI is reset, hold the RES pin low for at least 20 ms at power-up. To reset
during operation, hold the RES pin low for at least 20 states.
When the RES pin goes high after being held low for the necessary time, this LSI starts reset
exception handling as follows.
1. The internal state of the CPU and the registers of the on-chip supporting modules are
initialized, the T bit is cleared to 0 in EXR, and the I bit is set to 1 in EXR and CCR.
2. The reset exception handling vector address is read and transferred to the PC, and program
execution starts from the address indicated by the PC.
Figures 4-2 and 4-3 show examples of the reset sequence.
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