Table of Contents
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2.9
Basic Timing...................................................................................................................... 71
2.9.1
Overview............................................................................................................... 71
2.9.2
On-Chip Memory (ROM, RAM).......................................................................... 71
2.9.3
On-Chip Supporting Module Access Timing ....................................................... 73
2.9.4
On-Chip HCAN Module Access Timing.............................................................. 75
2.9.5
External Address Space Access Timing ............................................................... 76
2.10 Usage Note ......................................................................................................................... 76
2.10.1 TAS Instruction .................................................................................................... 76
2.10.2 Caution to observe when using bit manipulation instructions.............................. 76
Section 3
MCU Operating Modes ................................................................... 79
3.1
Overview............................................................................................................................ 79
3.1.1
Operating Mode Selection .................................................................................... 79
3.1.2
Register Configuration.......................................................................................... 80
3.2
Register Descriptions ......................................................................................................... 80
3.2.1
Mode Control Register (MDCR) .......................................................................... 80
3.2.2
System Control Register (SYSCR)....................................................................... 81
3.2.3
Pin Function Control Register (PFCR) ................................................................. 82
3.3
Operating Mode Descriptions ............................................................................................ 84
3.3.1
Mode 4 .................................................................................................................. 84
3.3.2
Mode 5 .................................................................................................................. 84
3.3.3
Mode 6 .................................................................................................................. 84
3.3.4
Mode 7 .................................................................................................................. 84
3.4
Pin Functions in Each Operating Mode ............................................................................. 85
3.5
Address Map in Each Operating Mode.............................................................................. 85
Section 4
Exception Handling ......................................................................... 89
4.1
Overview............................................................................................................................ 89
4.1.1
Exception Handling Types and Priority................................................................ 89
4.1.2
Exception Handling Operation ............................................................................. 90
4.1.3
Exception Vector Table ........................................................................................ 90
4.2
Reset................................................................................................................................... 92
4.2.1
Overview............................................................................................................... 92
4.2.2
Reset Sequence ..................................................................................................... 92
4.2.3
Interrupts after Reset............................................................................................. 94
4.2.4
State of On-Chip Supporting Modules after Reset Release.................................. 95
4.3
Traces ................................................................................................................................. 95
4.4
Interrupts ............................................................................................................................ 96
4.5
Trap Instruction.................................................................................................................. 97
4.6
Stack Status after Exception Handling .............................................................................. 98
4.7
Notes on Use of the Stack.................................................................................................. 99
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