Exception Handling Operation; Exception Vector Table - Hitachi H8S/2646 Hardware Manual

4.1.2

Exception Handling Operation

Exceptions originate from various sources. Trap instructions and interrupts are handled as follows:
1. The program counter (PC), condition code register (CCR), and extended register (EXR) are
pushed onto the stack.
2. The interrupt mask bits are updated. The T bit is cleared to 0.
3. A vector address corresponding to the exception source is generated, and program execution
starts from that address.
For a reset exception, steps 2 and 3 above are carried out.
4.1.3

Exception Vector Table

The exception sources are classified as shown in figure 4-1. Different vector addresses are
assigned to different exception sources.
Table 4-2 lists the exception sources and their vector addresses.
Reset
Trace
Exception
sources
Interrupts
Trap instruction
90
External interrupts: NMI, IRQ5 to IRQ0
Internal interrupts: Interrupts from on-chip supporting modules
43 sources in the H8S/2646, H8S/2646R,
and H8S/2645
47 sources in the H8S/2648, H8S/2648R,
and H8S/2647
Figure 4-1 Exception Sources