Hitachi H8S/2646 Hardware Manual page 1070

SSR0—Serial Status Register 0
Bit 7
TDRE
Initial value 1
Read/Write R/(W)
Transmit Data Register Empty
0 [Clearing conditions]
• When 0 is written in TDRE after reading TDRE = 1
• When the DTC is activated by a TXI interrupt and writes data to TDR
1 [Setting conditions]
• When the TE bit in SCR is 0
• When data is transferred from TDR to TSR and data can be written in TDR
1038
6 5
RDRF ORER
0 0
*9 *9 *9
R/(W) R/(W)
Framing Error
0 [Clearing condition]
1 [Setting condition]
Overrun Error
0 [Clearing condition]
When 0 is written in ORER after reading ORER = 1
1 [Setting condition]
When the next serial reception is completed while RDRF = 1
Receive Data Register Full
0 [Clearing conditions]
• When 0 is written in RDRF after reading RDRF = 1
• When the DTC is activated by an RXI interrupt and reads data from RDR
1 [Setting condition]
When serial reception ends normally and receive data is transferred from RSR to RDR
H'FF7C
4 3
FER PER
0 0
*9 *9
R/(W) R/(W)
Transmit End
0 [Clearing conditions]
• When 0 is written in TDRE after reading TDRE = 1
• When the DTC is activated by a TXI interrupt and
writes data to TDR
1 [Setting conditions]
• When the TE bit in SCR is 0
• When TDRE = 1 at transmission of the last bit of
a 1-byte serial transmit character
Parity Error
0 [Clearing condition]
When 0 is written in PER after reading PER = 1
1 [Setting condition]
When, in reception, the number of 1 bits in the receive
data plus the parity bit does not match the parity setting
(even or odd) specified by the O/E bit in SMR
When 0 is written in FER after reading FER = 1
When the SCI checks whether the stop bit at the end of the receive
data when reception ends, and the stop bit is 0
*8
2 1
TEND MPB MPBT
1 0
R R R/W
Multiprocessor Bit Transfer
0 Data with a 0 multi-processor
bit is transmitted
1 Data with a 1 multi-processor
bit is transmitted
Multiprocessor Bit
0 [Clearing condition]
When data with a 0 multiprocessor
bit is received
1 [Setting condition]
When data with a 1 multiprocessor
bit is received
*6
*4
*1
*2
SCI0
0
0
*7
*5
*3