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SCKCR—System Clock Control Register
Bit
7
PSTOP
Initial value
0
Read/Write
R/W
ø Clock Output Disable
DDR
PSTOP
Hardware standby mode
Software standby mode,
watch mode, and direct transition
Sleep mode and sub-sleep mode
High-speed mode, medium-speed
mode, and sub-active mode
6
5
—
—
0
0
—
—
System Clock Select
Frequency Multiplication Factor Switching Mode Select
0 Specified multiplication factor is valid after transition to software
standby mode, watch mode, or subactive mode
1 Specified multiplication factor is valid immediately after STC
bits are rewritten
H'FDE6
4
3
2
—
STCS
SCK2
0
0
0
—
R/W
R/W
0
0
0
Bus master in high-speed mode
1
Medium-speed clock is ø/2
1
0
Medium-speed clock is ø/4
1
Medium-speed clock is ø/8
1
0
0
Medium-speed clock is ø/16
1
Medium-speed clock is ø/32
1
—
—
0
1
—
0
High impedance
High impedance
High impedance
Fixed high
High impedance
ø output
High impedance
ø output
System
1
0
SCK1
SCK0
0
0
R/W
R/W
1
1
High impedance
Fixed high
Fixed high
Fixed high
961
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