Hitachi H8S/2646 Hardware Manual page 471

Bit 5—Parity Enable (PE): In asynchronous mode, selects whether or not parity bit addition is
performed in transmission, and parity bit checking in reception. In clocked synchronous mode
with a multiprocessor format, parity bit addition and checking is not performed, regardless of the
PE bit setting.
Bit 5
PE Description
0 Parity bit addition and checking disabled
1 Parity bit addition and checking enabled*
Note:* When the PE bit is set to 1, the parity (even or odd) specified by the O/E bit is added to
transmit data before transmission. In reception, the parity bit is checked for the parity (even
or odd) specified by the O/E bit.
Bit 4—Parity Mode (O/E): Selects either even or odd parity for use in parity addition and
checking.
The O/E bit setting is only valid when the PE bit is set to 1, enabling parity bit addition and
checking, in asynchronous mode. The O/E bit setting is invalid in clocked synchronous mode,
when parity addition and checking is disabled in asynchronous mode, and when a multiprocessor
format is used.
Bit 4
O/E Description
0 Even parity
1 Odd parity
Notes: *1 When even parity is set, parity bit addition is performed in transmission so that the total
number of 1 bits in the transmit character plus the parity bit is even.
In reception, a check is performed to see if the total number of 1 bits in the receive
character plus the parity bit is even.
*2 When odd parity is set, parity bit addition is performed in transmission so that the total
number of 1 bits in the transmit character plus the parity bit is odd.
In reception, a check is performed to see if the total number of 1 bits in the receive
character plus the parity bit is odd.
*1
* 2
(Initial value)
(Initial value)
439