Instructions That Disable Interrupts; Times When Interrupts Are Disabled - Hitachi H8S/2646 Hardware Manual

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Internal
address bus
Internal
write signal
TCIEV
TCFV
TCIV
interrupt signal
Figure 5-8 Contention between Interrupt Generation and Disabling
The above contention will not occur if an enable bit or interrupt source flag is cleared to 0 while
the interrupt is masked.
5.5.2

Instructions that Disable Interrupts

Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these
instructions is executed, all interrupts including NMI are disabled and the next instruction is
always executed. When the I bit is set by one of these instructions, the new value becomes valid
two states after execution of the instruction ends.
5.5.3

Times when Interrupts are Disabled

There are times when interrupt acceptance is disabled by the interrupt controller.
The interrupt controller disables interrupt acceptance for a 3-state period after the CPU has
updated the mask level with an LDC, ANDC, ORC, or XORC instruction.
124
TIER0 write cycle by CPU
TIER0 address
TCIV exception handling