Low-Power Control Register (Lpwrcr) - Hitachi H8S/2646 Hardware Manual

Bits 2 to 0—System clock select (SCK2 to SCK0): These bits select the bus master clock in
high-speed mode, medium-speed mode, and sub-active mode.
Set SCK2 to SCK0 all to 0 when shifting to operation in watch mode or sub-active mode.
Bit 2 Bit 1 Bit 0
SCK2 SCK1 SCK0
0 0 0
1
1 0
1
1 0 0
1
1 —
22.2.3

Low-Power Control Register (LPWRCR)

Bit :
DTON
Initial value :
R/W : R/W
The LPWRCR is an 8-bit read/write register that controls the low power dissipation modes.
The LPWRCR is initialized to H'00 at a reset and when in hardware standby mode. It is not
initialized in software standby mode. The following describes bits 7 to 2. For details of other bits,
see section 21.2.2, Low-Power Control Register (LPWRCR).
Bit 7—Direct Transition ON Flag (DTON): When shifting to low power dissipation mode by
executing the SLEEP instruction, this bit specifies whether or not to make a direct transition
between high-speed mode or medium-speed mode and the sub-active modes. The selected
operating mode after executing the SLEEP instruction is determined by the combination of other
control bits.
Description
Bus master in high-speed mode
Medium-speed clock is ø/2
Medium-speed clock is ø/4
Medium-speed clock is ø/8
Medium-speed clock is ø/16
Medium-speed clock is ø/32
—
7 6 5
LSON NESEL
0 0 0
R/W R/W
4 3
SUBSTP RFCUT
0 0
R/W R/W
(Initial value)
2 1
— STC1 STC0
0 0
R/W R/W R/W
0
0
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