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TXCR—Transmit Wait Cancel Register
Bit
15
TXCR7
Initial value
0
Read/Write
R/W
Bit
7
TXCR15
0
Initial value
R/W
Read/Write
Transmit Wait Cancel Register
TXACK—Transmit Acknowledge Register
Bit
15
TXACK7
Initial value
0
Read/Write
R/(W)*
7
Bit
TXACK15
0
Initial value
Read/Write
R/(W)*
Note: * Only 1 can be written, to clear the flag.
882
14
13
TXCR6
TXCR5
0
0
R/W
R/W
6
5
TXCR14
TXCR13
0
0
R/W
R/W
0
Transmit message cancellation idle state in corresponding mailbox
[Clearing condition]
Completion of TXPR clearing
(when transmit message is canceled normally)
1
TXPR cleared for corresponding mailbox
(transmit message cancellation)
14
13
TXACK6
TXACK5
0
0
R/(W)*
R/(W)*
6
5
TXACK14
TXACK13
0
0
R/(W)*
R/(W)*
H'F808
12
11
TXCR4
TXCR3
0
0
R/W
R/W
4
3
TXCR12
TXCR11
0
0
R/W
R/W
H'F80A
12
11
TXACK4
TXACK3
0
0
R/(W)*
R/(W)*
4
3
TXACK12
TXACK11
0
0
R/(W)*
R/(W)*
Transmit Acknowledge Register
0
[Clearing condition]
Writing 1
1
Completion of message transmission for
corresponding mailbox
10
9
TXCR2
TXCR1
0
0
R/W
R/W
2
1
TXCR10
TXCR9
0
0
R/W
R/W
10
9
TXACK2
TXACK1
0
0
R/(W)*
R/(W)*
2
1
TXACK10
TXACK9
TXACK8
0
0
R/(W)*
R/(W)*
HCAN
8
—
0
—
0
TXCR8
0
R/W
HCAN
8
—
0
—
0
0
R/(W)*
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