Bit Rate Register (Brr) - Hitachi H8S/2646 Hardware Manual

13.2.8

Bit Rate Register (BRR)

Bit :
Initial value :
R/W : R/W
BRR is an 8-bit register that sets the serial transmit/receive bit rate in accordance with the baud
rate generator operating clock selected by bits CKS1 and CKS0 in SMR.
BRR can be read or written to by the CPU at all times.
BRR is initialized to H'FF by a reset and in standby mode.
As baud rate generator control is performed independently for each channel, different values can
be set for each channel.
Table 13-3 shows sample BRR settings in asynchronous mode, and table 13-4 shows sample BRR
settings in clocked synchronous mode.
Table 13-3 BRR Settings for Various Bit Rates (Asynchronous Mode)
ø = 4 MHz
Bit Rate
(bit/s) n
110 2
150 1
300 1
600 0
1200 0
2400 0
4800 0
9600 0
19200 —
31250 0
38400 —
7 6 5
1 1 1
R/W R/W
ø = 4.9152 MHz
Error
N (%) n
70 0.03 2 86
207 0.16 1 255
103 0.16 1 127
207 0.16 0 255
103 0.16 0 127
51 0.16 0 63
25 0.16 0 31
12 0.16 0 15
— — 0
3 0.00 0 4
— — 0
4 3
1 1
R/W R/W
ø = 5 MHz
Error
N (%) n N
0.31 2 88
0.00 2 64
0.00 1 129
0.00 1 64
0.00 0 129
0.00 0 64
0.00 0 32
0.00 0 15
7 0.00 0 7
–1.70 0 4
3 0.00 0 3
2 1
1 1
R/W R/W R/W
ø = 6 MHz
Error
(%) n N
–0.25 2 106
0.16 2 77
0.16 1 155
0.16 1 77
0.16 0 155
0.16 0 77
–1.36 0 38
1.73 0 19
1.73 0 9
0.00 0 5
1.73 0 4
0
1
Error
(%)
–0.44
0.16
0.16
0.16
0.16
0.16
0.16
–2.34
–2.34
0.00
–2.34
449