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9.12.2
Register Configuration
Table 9-25 shows the port E register configuration.
Table 9-25 Port E Registers
Name
Port E data direction register
Port E data register
Port E register
Port E MOS pull-up control register
Note: * Lower 16 bits of the address.
Port E Data Direction Register (PEDDR)
Bit
:
7
PE7DDR PE6DDR PE5DDR PE4DDR PE3DDR PE2DDR PE1DDR PE0DDR
Initial value :
0
R/W
:
W
PEDDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port E. PEDDR cannot be read; if it is, an undefined value will be read.
PEDDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state by
a manual reset or in software standby mode.
Port E Data Register (PEDR)
Bit
:
7
PE7DR
Initial value :
0
R/W
:
R/W
PEDR is an 8-bit readable/writable register that stores output data for the port E pins (PE7 to PE0).
PEDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in
software standby mode.
Abbreviation
PEDDR
PEDR
PORTE
PEPCR
6
5
0
0
W
W
6
5
PE6DR
PE5DR
PE4DR
0
0
R/W
R/W
R/W
Initial Value
W
H'00
R/W
H'00
R
Undefined
R/W
H'00
4
3
0
0
W
W
4
3
PE3DR
PE2DR
0
0
R/W
R/W
R/W
Address *
H'FE3D
H'FF0D
H'FFBD
H'FE44
2
1
0
0
0
0
W
W
W
2
1
0
PE1DR
PE0DR
0
0
0
R/W
R/W
277
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