Pll Circuit; Medium-Speed Clock Divider; Bus Master Clock Selection Circuit - Hitachi H8S/2646 Hardware Manual

Hitachi 16-bit single-chip microcomputer h8s/2646 series

Table of Contents

PLL Circuit

The PLL circuit has the function of multiplying the frequency of the clock from the oscillator by a

factor of 1, 2, or 4. The multiplication factor is set with the STC bits in SCKCR. The phase of the

rising edge of the internal clock is controlled so as to match that at the EXTAL pin. The clock

frequency before and after multiplication must not exceed the maximum operating frequency

range of this LSI.

When the multiplication factor of the PLL circuit is changed, the operation varies according to the

setting of the STCS bit in SCKCR.

When STCS = 0 (initial value), the setting becomes valid after a transition to software standby

mode, watch mode, or subactive mode. The transition time count is performed in accordance with

the setting of bits STS2 to STS0 in SBYCR.

[1] The initial PLL circuit multiplication factor is 1.

[2] A value is set in bits STS2 to STS0 to give the specified transition time.

[3] The target value is set in STC1 and STC0, and a transition is made to software standby mode,

watch mode, or subactive mode.

[4] The clock pulse generator stops and the value set in STC1 and STC0 becomes valid.

[5] Software standby mode, watch mode, or subactive mode is cleared, and a transition time is

secured in accordance with the setting in STS2 to STS0.

[6] After the set transition time has elapsed, the LSI resumes operation using the target

multiplication factor.

If a PC break is set for the SLEEP instruction that causes a transition to software standby mode in

[1], software standby mode is entered and break exception handling is executed after the

oscillation stabilization time. In this case, the instruction following the SLEEP instruction is

executed after execution of the RTE instruction.

When STCS = 1, the LSI operates on the changed multiplication factor immediately after bits

STC1 and STC0 are rewritten.

The medium-speed clock divider divides the system clock to generate ø/2, ø/4, ø/8, ø/16, and ø/32.

The bus master clock selection circuit selects the system clock (ø) or one of the medium-speed

clocks (ø/2, ø/4, or ø/8, ø/16, and ø/32) to be supplied to the bus master, according to the settings

of the SCK2 to SCK0 bits in SCKCR.