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TCNT0—Timer Counter 0
Bit
7
Initial value
0
Read/Write
R/W
Note: TCNT is write-protected by a password to prevent accidental overwriting.
For details see section 12.2.4, Notes on Register Access.
RSTCSR—Reset Control/Status Register
Bit
7
WOVF
Initial value
0
Read/Write
R/(W)*
Watchdog Overflow Flag
0
[Clearing condition]
Cleared by reading TCSR when WOVF = 1, then writing 0 to WOVF
1
[Setting condition]
Set when TCNT overflows (changed from H'FF to H'00) during watchdog timer
operation
Note: * Can only be written with 0 for flag clearing.
RSTCSR is write-protected by a password to prevent accidential overwriting.
For details see section 12.2.4, Notes on Register Access.
1030
6
5
0
0
R/W
R/W
R/W
6
5
RSTE
—
0
0
R/W
—
Reset Enable
0
Reset signal is not generated if TCNT overflows*
1
Reset signal is generated if TCNT overflows
Note: * The modules within the H8S/2646 are not reset,
but TCNT and TCSR within the WDT are reset.
H'FF74(W), H'FF75(R)
4
3
2
0
0
0
R/W
R/W
Up-counter
H'FF76(W), H'FF77(R)
4
3
2
—
—
—
1
1
1
—
—
—
WDT0
1
0
0
0
R/W
R/W
WDT0
1
0
—
—
1
1
—
—
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