Hitachi H8S/2646 Hardware Manual page 919

MBIMR—Mailbox Interrupt Mask Register
Bit 15
MBIMR7
Initial value 1
Read/Write R/W
Bit 7
MBIMR15
1
Initial value
R/W
Read/Write
14 13
MBIMR6 MBIMR5 MBIMR4
1 1
R/W R/W
6 5
MBIMR14 MBIMR13 MBIMR12
1 1
R/W R/W
Mailbox Interrupt Mask
0 [Transmitting]
Interrupt request to CPU due to TXPR clearing
[Receiving]
Interrupt request to CPU due to RXPR setting
1 Interrupt requests to CPU disabled
H'F814
12 11 10
MBIMR3 MBIMR2
1 1
R/W R/W R/W
4 3
MBIMR11 MBIMR10
1 1
R/W R/W R/W
9 8
MBIMR1 MBIMR0
1 1 1
R/W R/W
2 1 0
MBIMR9 MBIMR8
1 1 1
R/W R/W
HCAN
887