Pwm Counters 1 And 2 (Pwcnt1, Pwcnt2); Pwm Cycle Registers 1 And 2 (Pwcyr1, Pwcyr2) - Hitachi H8S/2646 Hardware Manual

Hitachi 16-bit single-chip microcomputer h8s/2646 series

Table of Contents

PWM Counters 1 and 2 (PWCNT1, PWCNT2)

Initial value

PWCNT is a 10-bit up-counter incremented by the input clock. The input clock is selected by

clock select bits 2 to 0 (CKS2 to CKS0) in PWCR.

PWCNT1 is used as the channel 1 time base, and PWCNT2 as the channel 2 time base.

PWCNT is initialized to H'FC00 when the counter start bit (CST) in PWCR is cleared to 0, and

also upon reset and in standby mode, watch mode, subactive mode, subsleep mode, and module

Initial value

PWCYR is a 16-bit read/write register that sets the PWM conversion cycle. When a PWCYR

compare match occurs, PWCNT is cleared and data is transferred from the buffer register

(PWBFR) to the duty register (PWDTR). PWCYR1 is used for the channel 1 conversion cycle

setting, and PWCYR2 for the channel 2 conversion cycle setting.

PWCYR should be written to only while PWCNT is stopped. A value of H'FC00 must not be set.

PWCYR is initialized to H'FFFF upon reset, and in standby mode, watch mode, subactive mode,

subsleep mode, and module stop mode.

Compare match

(lower 10 bits)

(lower 10 bits)

— R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Figure 17-3 Cycle Register Compare Match

Compare match