Interrupt Priority Registers A To H, J, K, M (Ipra To Iprh, Iprj, Iprk, Iprm) - Hitachi H8S/2646 Hardware Manual

5.2.2

Interrupt Priority Registers A to H, J, K, M (IPRA to IPRH, IPRJ, IPRK, IPRM)

Bit : 7
—
Initial value : 0
—
R/W :
The IPR registers are eleven 8-bit readable/writable registers that set priorities (levels 7 to 0) for
interrupts other than NMI.
The correspondence between IPR settings and interrupt sources is shown in table 5-3.
The IPR registers set a priority (level 7 to 0) for each interrupt source other than NMI.
The IPR registers are initialized to H'77 by a reset and in hardware standby mode.
Bits 7 and 3—Reserved: These bits are always read as 0 and cannot be modified.
Table 5-3 Correspondence between Interrupt Sources and IPR Settings
Register
IPRA
IPRB
IPRC
IPRD
IPRE
IPRF
IPRG
IPRH
IPRJ
IPRK
IPRM
Notes: *1 Reserved. These bits are always read as 1 and cannot be modified.
*2 In the H8S/2646, H8S/2646R, and H8S/2645 these are reserved bits that are always
read as 1 and should only be written with H'7. In the H8S/2648, H8S/2648R, and
H8S/2647 these are the IPR bits for SCI channel 2.
6 5
IPR6 IPR5 IPR4
1 1
R/W R/W R/W
6 to 4
IRQ0
IRQ2
IRQ3
* 1
—
Watchdog timer 0
PC break
TPU channel 0
TPU channel 2
TPU channel 4
* 1
—
SCI channel 1
PWM channel 1, 2
4 3 2
— IPR2
1 0 1
— R/W
Bits
2 to 0
IRQ1
IRQ4
IRQ5
DTC
* 1
—
A/D converter, Watchdog timer 1
TPU channel 1
TPU channel 3
TPU channel 5
SCI channel 0
SCI channel 2 (H8S/2648R)
HCAN
1 0
IPR1 IPR0
1 1
R/W R/W
*2
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