Pwm Polarity Registers 1 And 2 (Pwpr1, Pwpr2) - Hitachi H8S/2646 Hardware Manual

Bits 7 to 0—Output Enable (OE): Each of these bits enables or disables the corresponding PWM
output.
Bits 7 to 0:
OE Description
0 PWM output is disabled
1 PWM output is enabled
17.2.3

PWM Polarity Registers 1 and 2 (PWPR1, PWPR2)

PWPR1
Bit 7
OPS1H
Initial value 0
Read/Write R/W
PWPR2
Bit 7
OPS2H
Initial value 0
Read/Write R/W
PWPR is an 8-bit read/write register that selects the PWM output polarity. PWPR1 controls
outputs PWM1H to PWM1A, and PWPR2 controls outputs PWM2H to PWM2A.
PWPR is initialized to H'00 upon reset, and in standby mode, watch mode, subactive mode,
subsleep mode, and module stop mode.
Bits 7 to 0—Output Polarity Select (OPS): Each of these bits selects the polarity of the
corresponding PWM output.
Bits 7 to 0:
OPS Description
0 PWM direct output
1 PWM inverse output
618
6 5
OPS1G OPS1F OPS1E
0 0
R/W R/W
6 5
OPS2G OPS2F OPS2E
0 0
R/W R/W
4 3
OPS1D OPS1C
0 0
R/W R/W R/W
4 3
OPS2D OPS2C
0 0
R/W R/W R/W
(Initial value)
2 1 0
OPS1B OPS1A
0 0 0
R/W R/W
2 1 0
OPS2B OPS2A
0 0 0
R/W R/W
(Initial value)