Hitachi H8S/2646 Hardware Manual page 204

Full access Burst access
T T T T T T T
1 2 3 1 2 1 2
ø
Low address only changes
Address bus
AS
RD
Data bus
Read data Read data Read data
Figure 7.14 (a) Example Burst ROM Access Timing (AST0=BRSTS1=1)
Full access Burst access
T T T T
1 2 1 1
ø
Low address only changes
Address bus
AS
RD
Data bus
Read data Read data Read data
Figure 7.14 (b) Example Burst ROM Access Timing (AST0=BRSTS1=0)
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