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TMDR0—Timer Mode Register 0
Bit
7
—
Initial value
1
Read/Write
—
6
5
4
—
BFB
BFA
1
0
0
—
R/W
R/W
Buffer Operation A
0
TGRA operates normally
1
TGRA and TGRC used together for buffer operation
Buffer Operation B
0
TGRB operates normally
1
TGRB and TGRD used together for buffer operation
H'FF11
3
2
MD3
MD2
0
0
R/W
R/W
Mode
0
0
0
0
Normal operation
1
Reserved
1
0
PWM mode 1
1
PWM mode 2
1
0
0
Phase counting mode 1
1
Phase counting mode 2
1
0
Phase counting mode 3
1
Phase counting mode 4
1
*
*
*
—
Notes: 1.
MD3 is a reserved bit. In a write,
it should always be written with 0.
2.
Phase counting mode cannot be
set for channel 0. In this case, 0
should always be written to MD2.
TPU0
1
0
MD1
MD0
0
0
R/W
R/W
*: Don't care
1011
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