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Write pulse application subroutine
Sub-Routine Write Pulse
WDT enable
Set PSU bit in FLMCR1
Wait (t
spsu
Set P bit in FLMCR1
Wait (t
sp
Clear P bit in FLMCR1
Wait (t
cp
Clear PSU bit in FLMCR1
Wait (t
cpsu
Disable WDT
End Sub
Note *6: Write Pulse Width
Write Time (tsp) µsec
Number of Writes n
1
2
3
4
5
6
7
8
9
10
11
12
13
998
999
1000
Note: Use a 10 µs write pulse for additional programming.
RAM
Program data storage
area (128 bytes)
Reprogram data storage
area (128 bytes)
Additional-programming
data storage area
(128 bytes)
Notes: *1 Data transfer is performed by byte transfer. The lower 8 bits of the first address written to must be H'00 or H'80.
A 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses.
*2 Verify data is read in 16-bit (word) units.
*3 Reprogram data is determined by the operation shown in the table below (comparison between the data stored in the program data area and the verify data). Bits for
which the reprogram data is 0 are programmed in the next reprogramming loop. Therefore, even bits for which programming has been completed will be subjected to
programming once again if the result of the subsequent verify operation is NG.
*4 A 128-byte area for storing program data, a 128-byte area for storing reprogram data, and a 128-byte area for storing additional data must be provided in RAM.
The contents of the reprogram data area and additional data area are modified as programming proceeds.
*5 A write pulse of 30 µs or 200 µs is applied according to the progress of the programming operation. See Note *6 for details of the pulse widths. When writing of
additional-programming data is executed, a 10 µs write pulse should be applied. Reprogram data X' means reprogram data when the write pulse is applied.
*7 The wait times and value of N are shown in section 23.7, Flash Memory characteristics.
Reprogram Data Computation Table
Original Data
(D)
0
0
1
1
Figure 20-11 Program/Program-Verify Flowchart (128-Byte Programming)
686
) µs
*
7
Start of programming
) µs
*
5
*
7
End of programming
) µs
*
7
) µs
*
7
Increment address
30
30
30
30
30
30
200
200
200
200
200
200
200
200
200
200
Successively write 128-byte data from additional-
programming data area in RAM to flash memory
Verify Data
Reprogram Data
(V)
(X)
0
1
Programming completed
1
0
Programming incomplete;
reprogram
0
1
1
1
Still in erased state; no action
Start of programming
START
Set SWE bit in FLMCR1
) µs
Wait (t
*
7
sswe
Store 128-byte program data in program
data area and reprogram data area
n= 1
m= 0
Write 128-byte data in RAM reprogram
data area consecutively to flash memory
Sub-Routine-Call
Write pulse
See Note *6 for pulse width
Set PV bit in FLMCR1
) µs
Wait (t
*
7
spv
H'FF dummy write to verify address
) µs
Wait (t
*
7
spvr
Read verify data
*
2
No
Write data =
verify data?
Yes
No
≥
6
n ?
Yes
Additional-programming data computation
Transfer additional-programming data to
additional-programming data area
*
3
Reprogram data computation
Transfer reprogram data to reprogram data area
128-byte
data verification completed?
No
Yes
Clear PV bit in FLMCR1
) µs
Wait (t
*
7
cpv
No
≥
6
n?
Yes
Sub-Routine-Call
Write Pulse (Additional programming)
No
m= 0 ?
Yes
Clear SWE bit in FLMCR1
) µs
Wait (t
cswe
End of programming
Additional-Programming Data Computation Table
Reprogram Data
Verify Data
Comments
(X')
(V)
0
0
0
1
1
0
1
1
Perform programming in the erased state.
Do not perform additional programming
on previously programmed addresses.
*
4
*
1
n ← n + 1
m = 1
*
4
*
4
Reprogram
*
1
*
7
No
n ≥ (N)?
Yes
Clear SWE bit in FLMCR1
) µs
Wait (t
cswe
*
7
Programming failure
Additional-
Comments
Programming Data (Y)
0
Additional programming
to be executed
1
Additional programming
not to be executed
1
Additional programming
not to be executed
Additional programming
1
not to be executed
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