Idle Cycle; Operation - Hitachi H8S/2646 Hardware Manual

7.6

Idle Cycle

7.6.1

Operation

When the H8S/2646 Series accesses external space , it can insert a 1-state idle cycle (T
bus cycles in the following two cases: (1) when read accesses between different areas occur
consecutively, and (2) when a write cycle occurs immediately after a read cycle. By inserting an
idle cycle it is possible, for example, to avoid data collisions between ROM, with a long output
floating time, and high-speed memory, I/O interfaces, and so on.
(1) Consecutive Reads between Different Areas
If consecutive reads between different areas occur while the ICIS1 bit in BCRH is set to 1, an idle
cycle is inserted at the start of the second read cycle.
Figure 7-15 shows an example of the operation in this case. In this example, bus cycle A is a read
cycle from ROM with a long output floating time, and bus cycle B is a read cycle from SRAM,
each being located in a different area. In (a), an idle cycle is not inserted, and a collision occurs in
cycle B between the read data from ROM and that from SRAM. In (b), an idle cycle is inserted,
and a data collision is prevented.
Bus cycle A
T
1
ø
Address bus
CS* (area A)
CS* (area B)
RD
Data bus
(a) Idle cycle not inserted
(ICIS1 = 0)
Note: * The CS signal is generated externally rather than inside the LSI device.
174
Bus cycle B
T T T T
2 3 1 2
Data
Long output
collision
floating time
Figure 7-15 Example of Idle Cycle Operation (1)
Bus cycle A
T
1
ø
Address bus
CS* (area A)
CS* (area B)
RD
Data bus
(b) Idle cycle inserted
) between
I
Bus cycle B
T T T T
2 3 I 1
(Initial value ICIS1 = 1)
T
2