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WCRL—Wait Control Register L
Bit
7
W31
Initial value
1
Read/Write
R/W
Area 2 Wait Control 1 and 0
0
0
1
1
0
1
Area 3 Wait Control 1 and 0
0
0
Program wait not inserted when external space area 3 is accessed
1
1 program wait state inserted when external space area 3 is accessed
1
0
2 program wait states inserted when external space area 3 is accessed
1
3 program wait states inserted when external space area 3 is accessed
6
5
W30
W21
1
1
R/W
R/W
Area 1 Wait Control 1 and 0
0
0
Program wait not inserted when external space area 1 is accessed
1
1 program wait state inserted when external space area 1 is accessed
1
0
2 program wait states inserted when external space area 1 is accessed
1
3 program wait states inserted when external space area 1 is accessed
Program wait not inserted when external space area 2 is accessed
1 program wait state inserted when external space area 2 is accessed
2 program wait states inserted when external space area 2 is accessed
3 program wait states inserted when external space area 2 is accessed
H'FED3
4
3
W20
W11
W10
1
1
R/W
R/W
R/W
Area 0 Wait Control 1 and 0
0
0
Program wait not inserted when external
space area 0 is accessed
1
1 program wait state inserted when external
space area 0 is accessed
1
0
2 program wait states inserted when external
space area 0 is accessed
1
3 program wait states inserted when external
space area 0 is accessed
Bus Controller
2
1
0
W01
W00
1
1
1
R/W
R/W
1005
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