Bus Control Register L (Bcrl) - Hitachi H8S/2646 Hardware Manual

Bit 4—Burst Cycle Select 1 (BRSTS1): Selects the number of burst cycles for the burst ROM
interface.
Bit 4
BRSTS1 Description
0 Burst cycle comprises 1 state
1 Burst cycle comprises 2 states
Bit 3—Burst Cycle Select 0 (BRSTS0): Selects the number of words that can be accessed in a
burst ROM interface burst access.
Bit 3
BRSTS0 Description
0 Max. 4 words in burst access
1 Max. 8 words in burst access
Bits 2 to 0—Reserved: Only 0 should be written to these bits.
7.2.5

Bus Control Register L (BCRL)

Bit :
Initial value :
R/W : R/W
BCRL is an 8-bit readable/writable register that performs selection of the external bus-released
state protocol, enabling or disabling of the write data buffer function.
BCRL is initialized to H'08 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 and 6—Reserved: Only 0 should be written to these bits.
Bit 5—Reserved: It is always read as 0. Cannot be written to.
Bit 4—Reserved: Only 0 should be written to this bit.
Bit 3—Reserved: Only 1 should be written to this bit.
Bit 2—Reserved: Only 0 should be written to this bit.
7 6 5
— — —
0 0 0
R/W —
4 3
— — —
0 1
R/W R/W R/W
(Initial value)
(Initial value)
2 1 0
WDBE WAITE
0 0 0
R/W R/W
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