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Table 5-10 Number of States in Interrupt Handling Routine Execution Statuses
Symbol
Instruction fetch
Branch address read
Stack manipulation
Legend
m: Number of wait states in an external device access.
5.5
Usage Notes
5.5.1
Contention between Interrupt Generation and Disabling
When an interrupt enable bit is cleared to 0 to disable interrupts, the disabling becomes effective
after execution of the instruction.
In other words, when an interrupt enable bit is cleared to 0 by an instruction such as BCLR or
MOV, if an interrupt is generated during execution of the instruction, the interrupt concerned will
still be enabled on completion of the instruction, and so interrupt exception handling for that
interrupt will be executed on completion of the instruction. However, if there is an interrupt
request of higher priority than that interrupt, interrupt exception handling will be executed for the
higher-priority interrupt, and the lower-priority interrupt will be ignored.
The same also applies when an interrupt source flag is cleared to 0.
Figure 5-8 shows an example in which the TCIEV bit in the TPU's TIER0 register is cleared to 0.
8 Bit Bus
Internal
2-State
Memory
Access
S
1
4
I
S
J
S
K
Object of Access
External Device
16 Bit Bus
3-State
2-State
Access
Access
6+2m
2
3-State
Access
3+m
123
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