Timer Status Register (Tsr) - Hitachi H8S/2646 Hardware Manual

10.2.5

Timer Status Register (TSR)

Channel 0: TSR0
Channel 3: TSR3
Bit : 7
—
Initial value : 1
R/W : —
Note: * Can only be written with 0 for flag clearing.
Channel 1: TSR1
Channel 2: TSR2
Channel 4: TSR4
Channel 5: TSR5
Bit : 7
TCFD
Initial value : 1
R/W : R
Note: * Can only be written with 0 for flag clearing.
The TSR registers are 8-bit registers that indicate the status of each channel. The TPU has six TSR
registers, one for each channel. The TSR registers are initialized to H'C0 by a reset, and in
hardware standby mode.
6 5
— — TCFV
1 0
— — R/(W)*
6 5
— TCFU TCFV
1 0
— R/(W)* R/(W)*
4 3 2
TGFD TGFC
0 0 0
R/(W)* R/(W)*
4 3 2
— —
0 0 0
— —
1 0
TGFB TGFA
0 0
R/(W)* R/(W)*
1 0
TGFB TGFA
0 0
R/(W)* R/(W)*
327