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LPWRCR—Low-Power Control Register
Bit
7
DTON
Initial value
0
Read/Write
R/W
Noise Elimination Sampling Frequency Select
Sampling using 1/32 ×ø
0
Sampling using 1/4 ×ø
1
Low-Speed ON Flag
• When the SLEEP instruction is executed in high-speed mode or medium-speed mode,
0
operation shifts to sleep mode, software standby mode, or watch mode*
• When the SLEEP instruction is executed in sub-active mode, operation shifts to watch
mode or shifts directly to high-speed mode
• Operation shifts to high-speed mode when watch mode is cancelled
• When the SLEEP instruction is executed in high-speed mode, operation shifts to watch
1
mode or sub-active mode
• When the SLEEP instruction is executed in sub-active mode, operation shifts to sub-
sleep mode or watch mode
• Operation shifts to sub-active mode when watch mode is cancelled
Note: * Always set high-speed mode when shifting to watch mode or sub-active mode.
Direct Transition ON Flag
• When the SLEEP instruction is executed in high-speed mode or medium-speed mode, operation shifts
0
to sleep mode, software standby mode, or watch mode*
• When the SLEEP instruction is executed in sub-active mode, operation shifts to sub-sleep mode or
watch mode
• When the SLEEP instruction is executed in high-speed mode or medium-speed mode, operation shifts
1
directly to sub-active mode*, or shifts to sleep mode or software standby mode
• When the SLEEP instruction is executed in sub-active mode, operation shifts directly to high-speed
mode, or shifts to sub-sleep mode
Note: * Always set high-speed mode when shifting to watch mode or sub-active mode.
964
6
5
LSON
NESEL
SUBSTP
0
0
R/W
R/W
R/W
Oscillation Circuit Feedback Resistance Control Bit
0
When the main clock is oscillating, sets the feedback
resistance ON. When the main clock is stopped, sets
the feedback resistance OFF
1
Sets the feedback resistance OFF
H'FDEC
4
3
2
RFCUT
—
0
0
0
R/W
R/W
Frequency Multiplication Factor
×1
0
0
×2
1
×4
1
0
1
Setting prohibited
Note: The clock frequency after a
multiplication must not exceed
the maximum operating
frequency of this LSI.
Subclock Enable
0
Enables subclock generation
1
Disables subclock generation
System
1
0
STC1
STC0
0
0
R/W
R/W
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