Erase Mode; Erase-Verify Mode - Hitachi H8S/2646 Hardware Manual

20.7.3

Erase Mode

When erasing flash memory, the single-block erase flowchart shown in figure 20-12 should be
followed.
The wait times after bits are set or cleared in the flash memory control register 1 (FLMCR1) and
the maximum number of erase operations (N) are shown in table 23-10 in section 23.7, Flash
Memory Characteristics.
To erase flash memory contents, make a 1-bit setting for the flash memory area to be erased in
erase block register 1 and 2 (EBR1, EBR2) at least (t
FLMCR1. Next, the watchdog timer (WDT) is set to prevent overerasing due to program
runaway, etc. Set a value greater than (t
Preparation for entering erase mode (erase setup) is performed next by setting the ESU bit in
FLMCR1. The operating mode is then switched to erase mode by setting the E bit in FLMCR1
after the elapse of at least (t
erase time. Ensure that the erase time does not exceed (t
Note: With flash memory erasing, preprogramming (setting all memory data in the memory to
be erased to all 0) is not necessary before starting the erase procedure.
20.7.4

Erase-Verify Mode

In erase-verify mode, data is read after memory has been erased to check whether it has been
correctly erased.
After the elapse of the fixed erase time, clear the E bit in FLMCR1, then wait for at least (t
before clearing the ESU bit to exit erase mode. After exiting erase mode, the watchdog timer
setting is also cleared. The operating mode is then switched to erase-verify mode by setting the
EV bit in FLMCR1. Before reading in erase-verify mode, a dummy write of H'FF data should be
made to the addresses to be read. The dummy write should be executed after the elapse of (t
or more. When the flash memory is read in this state (verify data is read in 16-bit units), the data at
the latched address is read. Wait at least (t
read operation. If the read data has been erased (all 1), a dummy write is performed to the next
address, and erase-verify is performed. If the read data is unerased, set erase mode again, and
repeat the erase/erase-verify sequence as before. The maximum number of repetitions of the
erase/erase-verify sequence is indicated by the maximum erase count (N). When verification is
completed, exit erase-verify mode, and wait for at least (t
all the erase blocks, clear the SWE bit in FLMCR1, and leave a wait time of at least (t
If erasing multiple blocks, set a single bit in EBR1/EBR2 for the next block to be erased, and
repeat the erase/erase-verify sequence as before.
) ms + (t
se
) µs. The time during which the E bit is set is the flash memory
sesu
) µs after the dummy write before performing this
sevr
) µs after setting the SWE bit to 1 in
sswe
+ t + t ) µs as the WDT overflow period.
sesu ce cesu
) ms.
se
) µs. If erasure has been completed on
cev
) µs
ce
) µs
sev
) µs.
cswe
687