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4.2.4
State of On-Chip Supporting Modules after Reset Release
After reset release, MSTPCRA to MSTPCRD are initialized to H'3F, H'FF, H'FF, and
*1
B'11******
, respectively, and all modules except the DTC, enter module stop mode.
Consequently, on-chip supporting module registers cannot be read or written to. Register reading
and writing is enabled when module stop mode is exited.
Note:
*1 The value of bits 5 to 0 is undefined.
4.3
Traces
Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control
mode 0, irrespective of the state of the T bit. For details of interrupt control modes, see section 5,
Interrupt Controller.
If the T bit in EXR is set to 1, trace mode is activated. In trace mode, a trace exception occurs on
completion of each instruction.
Trace mode is canceled by clearing the T bit in EXR to 0. It is not affected by interrupt masking.
Table 4-3 shows the state of CCR and EXR after execution of trace exception handling.
Interrupts are accepted even within the trace exception handling routine.
The T bit saved on the stack retains its value of 1, and when control is returned from the trace
exception handling routine by the RTE instruction, trace mode resumes.
Trace exception handling is not carried out after execution of the RTE instruction.
Table 4-3
Status of CCR and EXR after Trace Exception Handling
Interrupt Control Mode
0
2
Legend
1:
Set to 1
0:
Cleared to 0
—: Retains value prior to execution.
*:
Trace exception handling cannot be used.
CCR
I
UI
*
*
1
—
EXR
I2 to I0
T
*
*
—
0
95
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