Hitachi H8S/2646 Hardware Manual page 871

Figure A-1 shows timing waveforms for the address bus and the RD, HWR, and LWR signals
during execution of the above instruction with an 8-bit bus, using three-state access with no wait
states.
ø
Address bus
RD
HWR, LWR
of instruction
Figure A-1 Address Bus, RD, HWR, and LWR Timing
R:W 2nd
Fetching Fetching
3rd byte 4th byte
of instruction
(8-Bit Bus, Three-State Access, No Wait States)
High level
Internal
R:W EA
operation
Fetching
1nd byte of
instruction at
jump address
Fetching
2nd byte of
instruction at
jump address
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