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(2) Write after Read
If an external write occurs after an external read while the ICIS0 bit in BCRH is set to 1, an idle
cycle is inserted at the start of the write cycle.
Figure 7-16 shows an example of the operation in this case. In this example, bus cycle A is a read
cycle from ROM with a long output floating time, and bus cycle B is a CPU write cycle. In (a), an
idle cycle is not inserted, and a collision occurs in cycle B between the read data from ROM and
the CPU write data. In (b), an idle cycle is inserted, and a data collision is prevented.
Bus cycle A
T
1
ø
Address bus
CS* (area A)
CS* (area B)
RD
Possibility of overlap between
CS (area B) and RD
(a) Idle cycle not inserted
(ICIS1 = 0)
Note: * The CS signal is generated externally rather than inside the LSI device.
Bus cycle B
T
T
T
T
2
3
1
2
Figure 7-16 Example of Idle Cycle Operation (2)
Bus cycle A
T
1
ø
Address bus
CS* (area A)
CS* (area B)
RD
(b) Idle cycle inserted
Bus cycle B
T
T
T
T
2
3
I
1
(Initial value ICIS1 = 1)
T
2
175
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