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If a SLEEP instruction is executed when the SSBY bit in SBYCR is cleared to 0, and LSON bit in
LPWRCR is cleared to 0, a transition is made to sleep mode. When sleep mode is cleared by an
interrupt, medium-speed mode is restored.
When the SLEEP instruction is executed with the SSBY bit = 1, LPWRCR LSON bit = 0, and
TCSR (WDT1) PSS bit = 0, operation shifts to the software standby mode. When software
standby mode is cleared by an external interrupt, medium-speed mode is restored.
When the RES pin is set low and medium-speed mode is cancelled, operation shifts to the reset
state. The same applies in the case of a reset caused by overflow of the watchdog timer.
When the STBY pin is driven low, a transition is made to hardware standby mode.
Figure 22-2 shows the timing for transition to and clearance of medium-speed mode.
ø,
supporting module clock
Bus master clock
Internal address bus
Internal write signal
Figure 22-2 Medium-Speed Mode Transition and Clearance Timing
22.4
Sleep Mode
22.4.1
Sleep Mode
When the SLEEP instruction is executed when the SBYCR SSBY bit = 0 and the LPWRCR
LSON bit = 0, the CPU enters the sleep mode. In sleep mode, CPU operation stops but the
contents of the CPU's internal registers are retained. Other supporting modules do not stop.
22.4.2
Exiting Sleep Mode
Sleep mode is exited by any interrupt, or signals at the RES, or STBY pins.
SBYCR
Medium-speed mode
SBYCR
739
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