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TIOR4—Timer I/O Control Register 4
Bit
7
IOB3
Initial value
0
Read/Write
R/W
TGR4B I/O Control
0
0
0
0
TGR4B is
output
1
compare
1
0
register
1
1
0
0
1
1
0
1
1
0
0
0
TGR4B is
input
1
capture
1
*
register
1
*
*
6
5
IOB2
IOB1
0
0
R/W
R/W
TGR4A I/O Control
0
0
0
0
TGR4A is
output
1
compare
1
0
register
1
1
0
0
1
1
0
1
1
0
0
0
TGR4A is
input
1
capture
1
*
register
1
*
*
Output disabled
Initial output is 0
0 output at compare match
output
1 output at compare match
Toggle output at compare match
Output disabled
Initial output is 1
0 output at compare match
output
1 output at compare match
Toggle output at compare match
Capture input
Input capture at rising edge
source is
Input capture at falling edge
TIOCB4 pin
Input capture at both edges
Capture input
Input capture at generation of TGR3C
source is TGR3C
compare match/input capture
compare match/
input capture
H'FE92
4
3
IOB0
IOA3
IOA2
0
0
R/W
R/W
R/W
Output disabled
Initial output is 0
0 output at compare match
output
1 output at compare match
Toggle output at compare match
Output disabled
Initial output is 1
0 output at compare match
output
1 output at compare match
Toggle output at compare match
Capture input
Input capture at rising edge
source is
Input capture at falling edge
TIOCA4 pin
Input capture at both edges
Capture input
Input capture at generation of TGR3A
source is TGR3A
compare match/input capture
compare match/
input capture
*: Don't care
2
1
0
IOA1
IOA0
0
0
0
R/W
R/W
*: Don't care
TPU4
991
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