Message Control (Mc0 To Mc15) - Hitachi H8S/2646 Hardware Manual

LAFMH Bits 12 to 10—Reserved: These bits always read 0. The write value should always be 0.
LAFMH Bits 9 and 8, LAFML bits 15 to 0–18-Bit Identifier Filter (LAFMHx, LAFMLx):
Filter mask bits for the 18 bits of the receive message identifier (extended).
Bit x: LAFMHx
LAFMLx
0
1

15.2.18 Message Control (MC0 to MC15)

The message control register sets (MC0 to MC15) consist of eight 8-bit readable/writable registers
(MCx[1] to MCx[8]). The HCAN has 16 sets of these registers (MC0 to MC15).
The initial value of these registers is undefined, so they must be initialized (by writing 0 or 1).
MCx [1]
Bit:
Initial value:
R/W:
MCx [2]
Bit:
Initial value:
R/W:
MCx [3]
Bit:
Initial value:
R/W:
Description
Stored in RX0 (receive-only mailbox) depending on bit match between RX0
message identifier and receive message identifier
Stored in RX0 (receive-only mailbox) regardless of bit match between RX0
message identifier and receive message identifier
7 6
— —
* *
— —
7 6
— —
* *
R/W R/W R/W
7 6
— —
* *
R/W R/W R/W
5 4 3
— — DLC3
* * *
— — —
5 4 3
— — —
* * *
R/W R/W
5 4 3
— — —
* * *
R/W R/W
(Initial value)
(x = 15 to 0)
2 1
DLC2 DLC1 DLC0
* *
— —
2 1
— —
* *
R/W R/W R/W
2 1
— —
* *
R/W R/W R/W
*:Undefined
0
*
—
0
—
*
0
—
*
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