Table of Contents
Advertisement
Reset state
Program execution state
High-speed mode
(main clock)
SCK2 to
SCK0= 0
Medium-speed
(main clock)
SLEEP instruction
SSBY = 1, PSS = 1
DTON = 1, LSON = 0
After the oscillation
stabilization time
(STS2 to 0), clock
switching exception
processing
Sub-active mode
(subclock)
Notes: *1 NMI, IRQ0 to IRQ5, and WDT1 interrupts
*2 NMI, IRQ0 to IRQ5, IWDT0 interrupts, and WDT1 interrupt.
*3 All interrupts
*4 NMI and IRQ0 to IRQ5
• When a transition is made between modes by means of an interrupt, the transition cannot be made
on interrupt source generation alone. Ensure that interrupt handling is performed after accepting the
interrupt request.
• From any state except hardware standby mode, a transition to the reset state occurs when RES is
driven Low.
• From any state, a transition to hardware standby mode occurs when STBY is driven low.
• Always select high-speed mode before making a transition to watch mode or sub-active mode.
STBY pin = High
RES pin = Low
RES pin = High
SCK2 to
SCK0≠ 0
mode
SLEEP instruction
SSBY = 1, PSS = 1
DTON = 1, LSON = 1
Clock switching
exception processing
: Transition after exception processing
Figure 22-1 Mode Transition Diagram
SLEEP instruction
Any interrupt *
3
SLEEP
instruction
External
interrupt *
4
SLEEP
instruction
Interrupt *
1
LSON bit = 0
SLEEP
instruction
1
Interrupt *
LSON bit = 1
SLEEP instruction
2
Interrupt *
Program-halted state
STBY pin = Low
Hardware
standby mode
SSBY= 0, LSON= 0
Sleep mode
(main clock)
SSBY= 1,
PSS= 0, LSON= 0
Software
standby mode
SSBY= 1,
PSS= 1, DTON= 0
Watch mode
(subclock)
SSBY= 0,
PSS= 1, LSON= 1
Sub-sleep mode
(subclock)
: Low power dissipation mode
727
Advertisement
Table of Contents
