Pwm Buffer Registers 2A To 2D (Pwbfr2A To Pwbfr2D) - Hitachi H8S/2646 Hardware Manual

17.2.9

PWM Buffer Registers 2A to 2D (PWBFR2A to PWBFR2D)

Bit 15 14
— —
Initial value 1 1
Read/Write — —
There are four 16-bit read/write PWBFR2 registers (PWBFR2A to PWBFR2D). When a
PWCYR2 compare match occurs, data is transferred from PWBFR2A to PWDTR2A or
PWDTR2E, from PWBFR2B to PWDTR2B or PWDTR2F, from PWBFR2C to PWDTR2C or
PWDTR2G, and from PWBFR2D to PWDTR2D or PWDTR2H. The transfer destination is
determined by the value of the TDS bit.
PWBFR2 is initialized to H'EC00 upon reset, and in standby mode, watch mode, subactive mode,
subsleep mode, and module stop mode.
Bits 15 to 13—Reserved: These bits are always read as 1 and cannot be modified.
Bit 12—Transfer Destination Select (TDS): Bit 12 selects the PWDTR2 register to which data is
to be transferred.
Register Bit 12: TDS
PWBFR2A 0
1
PWBFR2B 0
1
PWBFR2C 0
1
PWBFR2D 0
1
Bits 11 and 10—Reserved: These bits are always read as 1 and cannot be modified.
Bits 9 to 0—Duty (DT): Bits 9 to 0 comprise the data transferred to bits 9 to 0 in PWDTR2.
624
13 12 11 10
— TDS — — DT9 DT8 DT7 DT6 DT5 DT4 DT3 DT2 DT1 DT0
1 0 1 1
— R/W — — R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Description
PWDTR2A selected
PWDTR2E selected
PWDTR2B selected
PWDTR2F selected
PWDTR2C selected
PWDTR2G selected
PWDTR2D selected
PWDTR2H selected
9 8 7 6
0 0 0 0
5 4 3 2
0 0 0 0
(Initial value)
(Initial value)
(Initial value)
(Initial value)
1 0
0 0