Dtc Source Address Register (Sar); Dtc Destination Address Register (Dar); Dtc Transfer Count Register A (Cra) - Hitachi H8S/2646 Hardware Manual

8.2.3

DTC Source Address Register (SAR)

Bit : 23 22
Initial value :
*
— —
R/W :
SAR is a 24-bit register that designates the source address of data to be transferred by the DTC.
For word-size transfer, specify an even source address.
8.2.4

DTC Destination Address Register (DAR)

Bit : 23
Initial value :
*
R/W : —
DAR is a 24-bit register that designates the destination address of data to be transferred by the
DTC. For word-size transfer, specify an even destination address.
8.2.5

DTC Transfer Count Register A (CRA)

Bit : 15 14
Initial value :
*
— —
R/W :
CRA is a 16-bit register that designates the number of times data is to be transferred by the DTC.
In normal mode, the entire CRA functions as a 16-bit transfer counter (1 to 65,536). It is
decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000.
21 20 19
* * * *
— — —
22 21 20 19
* * * *
— — — —
13 12 11 10
* * * *
— — — —
CRAH
9 8 7
* * * *
— — — —
4 3
* *
— — —
4 3
* *
— —
6 5 4 3
* * * *
— — — —
CRAL
2 1 0
* * *
— —
*: Undefined
2 1 0
* * *
— — —
*: Undefined
2 1 0
* * *
— —
*: Undefined
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