Interrupt Interface - Hitachi H8S/2646 Hardware Manual

HCAN halt mode is entered by setting the halt request bit (MCR1) to 1 in the master control
register (MCR). If the CAN bus is operating, the transition to HCAN halt mode is delayed until
the bus becomes idle.
HCAN halt mode is cleared by clearing MCR1 to 0.
15.3.7

Interrupt Interface

There are 12 HCAN interrupt sources, to which five independent interrupt vectors are assigned.
Table 15-5 lists the HCAN interrupt sources.
With the exception of the reset processing vector (IRR0), these sources can be masked. Masking is
implemented using the mailbox interrupt mask register (MBIMR) and interrupt mask register
(IMR).
Table 15-5 HCAN Interrupt Sources
IPR Bits Vector
IPRM (2–0) ERS0
OVR0
RM0
RM1
SLE0
Vector Number IRR Bit
108 IRR5
IRR6
108 IRR0
IRR2
IRR3
IRR4
IRR7
IRR9
IRR12
109 IRR1
108 IRR1
108 IRR8
Description
Error passive interrupt (TEC ≥ 128 or REC ≥
128)
Bus off interrupt (TEC ≥ 256)
Reset processing interrupt
Remote frame reception interrupt
Error warning interrupt (TEC ≥ 96)
Error warning interrupt (REC ≥ 96)
Overload frame transmission interrupt
Unread message overwrite interrupt
HCAN sleep mode CAN bus operation
interrupt
Mailbox 0 message reception interrupt
Mailbox 1-15 message reception interrupt
Message transmission/cancellation interrupt
583