Hitachi H8S/2646 Hardware Manual page 453

WDT1 Input Clock Select
Bit 4 Bit 2 Bit 1
PSS CKS2 CKS1
0 0 0
1
1 0
1
1 0 0
1
1 0
1
Note: * An overflow period is the time interval between the start of counting up from H'00 on the
TCNT and the occurrence of a TCNT overflow.
Description
Bit 0
CKS0 Clock
0 ø/2 (initial value)
1 ø/64
0 ø/128
1 ø/512
0 ø/2048
1 ø/8192
0 ø/32768
1 ø/131072
0 øSUB/2
1 øSUB/4
0 øSUB/8
1 øSUB/16
0 øSUB/32
1 øSUB/64
0 øSUB/128
1 øSUB/256
Overflow Period* (where ø = 20 MHz)
(where ø SUB = 32.768 kHz)
25.6 µs
819.2 µs
1.6 ms
6.6 ms
26.2 ms
104.9 ms
419.4 ms
1.68 s
15.6 ms
31.3 ms
62.5 ms
125 ms
250 ms
500 ms
1 s
2 s
421