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IER—IRQ Enable Register
Bit
7
—
Initial value
0
R/W
Read/Write
ISR—IRQ Status Register
Bit
7
—
Initial value
0
Read/Write
R/(W)*
IRQ5 to IRQ0 Flags
0
1
Note: * Only 0 can be written, to clear the flag.
968
6
5
—
IRQ5E
0
0
R/W
R/W
IRQ5 to IRQ0 Enable
0
1
6
5
—
IRQ5F
0
0
R/(W)*
R/(W)*
[Clearing conditions]
• Cleared by reading IRQnF when IRQnF = 1, then writing 0 to IRQnF flag
• When interrupt exception handling is executed while low-level detection
is set (IRQnSCB = IRQnSCA = 0) and IRQn input is high
• When IRQn interrupt exception handling is executed while falling, rising,
or both-edge detection is set (IRQnSCB = 1 or IRQnSCA = 1)
• When the DTC is activated by an IRQn interrupt, and the DISEL bit in
MRB of the DTC is cleared to 0
[Setting conditions]
• When IRQn input goes low when low-level detection is set
(IRQnSCB = IRQnSCA = 0)
• When a falling edge occurs in IRQn input when falling edge detection is
set (IRQnSCB = 0, IRQnSCA = 1)
• When a rising edge occurs in IRQn input when rising edge detection is
set (IRQnSCB = 1, IRQnSCA = 0)
• When a falling or rising edge occurs in IRQn input when both-edge
detection is set (IRQnSCB = IRQnSCA = 1)
H'FE14
4
3
IRQ4E
IRQ3E
0
0
R/W
R/W
IRQn interrupts disabled
IRQn interrupts enabled
(n = 5 to 0)
H'FE15
4
3
IRQ4F
IRQ3F
0
0
R/(W)*
R/(W)*
Interrupt Controller
2
1
IRQ2E
IRQ1E
IRQ0E
0
0
R/W
R/W
Interrupt Controller
2
1
IRQ2F
IRQ1F
IRQ0F
0
0
R/(W)*
R/(W)*
R/(W)*
(n = 5 to 0)
0
0
R/W
0
0
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