Usage Note - Hitachi H8S/2646 Hardware Manual

Hitachi 16-bit single-chip microcomputer h8s/2646 series

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H'000. The CMF bit in PWCR2 is set, and if the IE bit in PWCR2 has been set, an interrupt can be

requested or the DTC can be activated.

Stopping: When the CST bit in PWCR2 is cleared to 0, PWCNT2 is reset and stops. PWDTR2A

to PWDTR2H are reset. All PWM outputs go low (or high if the corresponding bit in PWPR2 is

Usage Note

Contention between Buffer Register Write and Compare Match

If a PWBFR write is performed in the state immediately after a cycle register compare match, the

buffer register and duty register are overwritten. PWM output changed by the cycle register

compare match is not changed in the overwrite of the duty register due to contention. This may

result in unanticipated duty output. In the case of channel 2, the duty register used as the transfer

destination is selected by the TDS bit of the buffer register when an overwrite of the duty register

occurs due to contention. This can also result in an unintended overwrite of the duty register.

Buffer register rewriting must be completed before automatic transfer by the DTC (data transfer

controller), exception handling due to a compare match interrupt, or the occurrence of a cycle

Write signal

(lower 10 bits)

Buffer register address

Compare match

Figure 17-12 PWM Channel 1 Operation