Hitachi H8S/2646 Hardware Manual page 451

WDT0 Mode Select
TCSR0
WT/IT Description
0 Interval timer mode: WDT0 requests an interval timer interrupt (WOVI)
from the CPU when the TCNT overflows.
1 Watchdog timer mode: A reset is issued when the TCNT overflows if the RSTE bit of
RSTCSR is set to 1.*
Note: * For details see section 12.2.3, Reset Control/Status Register (RSTCSR).
WDT1 Mode Select
TCSR1
WT/IT Description
0 Interval timer mode: WDT1 requests an interval timer interrupt (WOVI)
from the CPU when the TCNT overflows.
1 Watchdog timer mode: WDT1 requests a reset or an NMI interrupt from
the CPU when the TCNT overflows.
Bit 5—Timer Enable (TME): Selects whether TCNT runs or is halted.
Bit 5
TME Description
0 TCNT is initialized to H'00 and halted
1 TCNT counts
WDT0 TCSR Bit 4—Reserved Bit: It is always read as 1 and cannot be modified.
WDT1 TCSR Bit 4—Prescaler Select (PSS): This bit is used to select an input clock source for
the TCNT of WDT1.
See the descriptions of Clock Select 2 to 0 for details.
Bit 4
PSS Description
0 The TCNT counts frequency-division clock pulses of the ø based
prescaler (PSM).
1 The TCNT counts frequency-division clock pulses of the ø SUB-based prescaler
(PSS).
(Initial value)
(Initial value)
(Initial value)
(Initial value)
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