Table of Contents
Advertisement
Empty bits in these registers (bits with no corresponding module, see table 22-4, should always be
written with 1.
MSTPCRA Bits 7 to 0, MSTPCRB Bits 7 to 0, MSTPCRC Bits 7 and 5 to 0, MSTPCRD Bits
7 and 6—Module Stop (MSTPA7 to MSTPA0, MSTPB7, MSTPB6, and MSTPB4 to
MSTPB0, MSTPC7, and MSTPC5 to MSTPC0, MSTPD7, and MSTPD6): These bits specify
module stop mode. See table 22-4 for the method of selecting the on-chip peripheral functions.
MSTPA7 to MSTPA0,
MSTPB7, MSTPB6, and
MSTPB4 to MSTPB0
MSTPC7, and MSTPC5
to MSTPC0
MSTPD7 and MSTPD6 Description (H8S/2646, H8S/2646R, H8S/2645)
0
1
MSTPA7 to MSTPA0,
MSTPB7 to MSTPB0
MSTPC7, and MSTPC5
to MSTPC0
MSTPD7 and MSTPD6 Description (H8S/2648, H8S/2648R, H8S/2647)
0
1
22.3
Medium-Speed Mode
In high-speed mode, when the SCK2 to SCK0 bits in SCKCR are set to 1, the operating mode
changes to medium-speed mode as soon as the current bus cycle ends. In medium-speed mode, the
CPU operates on the operating clock (ø/2, ø/4, ø/8, ø/16, or ø/32) specified by the SCK2 to SCK0
bits. The bus masters other than the CPU (DTC) also operate in medium-speed mode. On-chip
supporting modules other than the bus masters always operate on the high-speed clock (ø).
In medium-speed mode, a bus access is executed in the specified number of states with respect to
the bus master operating clock. For example, if ø/4 is selected as the operating clock, on-chip
memory is accessed in 4 states, and internal I/O registers in 8 states.
Medium-speed mode is cleared by clearing all of bits SCK2 to SCK0 to 0. A transition is made to
high-speed mode and medium-speed mode is cleared at the end of the current bus cycle.
738
Module stop mode is cleared (initial value of MSTPA7 and MSTPA6)
Module stop mode is set (initial value of MSTPA5 to 0, MSTPB7 to 0,
MSTPC7 to 0, and MSTPD7, 6)
Module stop mode is cleared (initial value of MSTPA7 and MSTPA6)
Module stop mode is set (initial value of MSTPA5 to 0, MSTPB7 to 0,
MSTPC7 to 0, and MSTPD7, 6)
Advertisement
Table of Contents
