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15.2.11 Interrupt Register (IRR)
The interrupt register (IRR) is a 16-bit readable/writable register containing status flags for the
various interrupt sources.
IRR
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
Note: * Only a write of 1 is permitted, to clear the flag.
Bit 15—Overload Frame Interrupt Flag: Status flag indicating that the HCAN has transmitted
an overload frame.
Bit 15: IRR7
0
1
Bit 14—Bus Off Interrupt Flag: Status flag indicating the bus off state caused by the transmit
error counter.
Bit 14: IRR6
0
1
15
14
IRR7
IRR6
IRR5
0
0
R/(W)*
R/(W)*
R/(W)*
7
6
—
—
0
0
—
—
Description
[Clearing condition]
Writing 1
Overload frame transmission
[Setting conditions]
When overload frame is transmitted
Description
[Clearing condition]
Writing 1
Bus off state caused by transmit error
[Setting condition]
When TEC ≥ 256
13
12
11
IRR4
IRR3
0
0
0
R/(W)*
R/(W)*
5
4
3
—
IRR12
—
0
0
0
—
R/(W)*
—
10
9
IRR2
IRR1
IRR0
0
0
R
R
R/(W)*
2
1
—
IRR9
IRR8
0
0
—
R
R/(W)*
(Initial value)
(Initial value)
8
1
0
0
547
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