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TIOR3L—Timer I/O Control Register 3L
Bit
7
IOD3
Initial value
0
Read/Write
R/W
TGR3D I/O Control
0
0
0
0
TGR3D is
output
1
compare
1
0
register
1
1
0
0
1
1
0
1
1
0
0
0
TGR3D is
input
1
capture
1
*
register
1
*
*
Notes: *1
When bits TPSC2 to TPSC0 in TCR4 are set to B'000 and ø/1 is used as the
TCNT4 count clock, this setting is invalid and input capture is not generated.
When the BFB bit in TMDR3 is set to 1 and TGR3D is used as a buffer register,
*2
this setting is invalid and input capture/output compare is not generated.
Note: When TGRC or TGRD is designated for buffer operation, this setting is invalid and the
register operates as a buffer register.
6
5
IOD2
IOD1
0
0
R/W
R/W
TGR3C I/O Control
0
0
0
0
TGR3C is
output
1
compare
1
0
*1
register
1
1
0
0
1
1
0
1
1
0
0
0
TGR3C is
input
1
capture
1
*
*1
register
1
*
*
Note: *1 When the BFA bit in TMDR3 is set to 1 and TGR3C is used as a buffer register,
this setting is invalid and input capture/output compare is not generated.
Output disabled
Initial output is 0
0 output at compare match
output
1 output at compare match
*2
Toggle output at compare match
Output disabled
Initial output is 1
0 output at compare match
output
1 output at compare match
Toggle output at compare match
Capture input
Input capture at rising edge
source is
Input capture at falling edge
TIOCD3 pin
Input capture at both edges
*2
Capture input
Input capture at TCNT4 count-up/
source is channel
count-down
4/count clock
H'FE83
4
3
IOD0
IOC3
IOC2
0
0
R/W
R/W
R/W
Output disabled
Initial output is 0
0 output at compare match
output
1 output at compare match
Toggle output at compare match
Output disabled
Initial output is 1
0 output at compare match
output
1 output at compare match
Toggle output at compare match
Capture input
Input capture at rising edge
source is
Input capture at falling edge
TIOCC3 pin
Input capture at both edges
Capture input
Input capture at TCNT4 count-up/
source is channel
count-down
4/count clock
*1
*: Don't care
2
1
0
IOC1
IOC0
0
0
0
R/W
R/W
*: Don't care
TPU3
985
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