Pwm Buffer Registers 1A, 1C, 1E, 1G (Pwbfr1A, 1C, 1E, 1G); Pwm Duty Registers 2A To 2H (Pwdtr2A To Pwdtr2H) - Hitachi H8S/2646 Hardware Manual

Hitachi 16-bit single-chip microcomputer h8s/2646 series

Table of Contents

PWM Buffer Registers 1A, 1C, 1E, 1G (PWBFR1A, 1C, 1E, 1G)

Initial value

There are four 16-bit read/write PWBFR1 registers (PWBFR1A, 1C, 1E, 1G). When a PWCYR1

compare match occurs, data is transferred from PWBFR1A to PWDTR1A, from PWBFR1C to

PWDTR1C, from PWBFR1E to PWDTR1E, and from PWBFR1G to PWDTR1G.

PWBFR1 is initialized to H'EC00 upon reset, and in standby mode, watch mode, subactive mode,

subsleep mode, and module stop mode.

Bits 15 to 13—Reserved: These bits are always read as 1 and cannot be modified.

Bit 12—Output Terminal Select (OTS): Bit 12 is the data transferred to bit 12 of PWDTR1.

Bits 11 and 10—Reserved: These bits are always read as 1 and cannot be modified.

Bits 9 to 0—Duty (DT): Bits 9 to 0 comprise the data transferred to bits 9 to 0 in PWDTR1.

Initial value

There are eight PWDTR2 registers (PWDTR2A to PWDTR2H). PWDTR2A is used for output

PWM2A, PWDTR2B for output PWM2B, PWDTR2C for output PWM2C, PWDTR2D for output

PWM2D, PWDTR2E for output PWM2E, PWDTR2F for output PWM2F, PWDTR2G for output

PWM2G, and PWDTR2H for output PWM2H.

PWDTR2 cannot be read or written to directly. When a PWCYR2 compare match occurs, data is

transferred from buffer register 2 (PWBFR2) to PWDTR2.

PWDTR2 is initialized to H'EC00 when the counter start bit (CST) in PWCR2 is cleared to 0, and

also upon reset and in standby mode, watch mode, subactive mode, subsleep mode, and module

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