Hitachi H8S/2646 Hardware Manual page 342

Bit 4—Buffer Operation A (BFA): Specifies whether TGRA is to operate in the normal way, or
TGRA and TGRC are to be used together for buffer operation. When TGRC is used as a buffer
register, TGRC input capture/output compare is not generated.
In channels 1, 2, 4, and 5, which have no TGRC, bit 4 is reserved. It is always read as 0 and cannot
be modified.
Bit 4
BFA Description
0 TGRA operates normally
1 TGRA and TGRC used together for buffer operation
Bits 3 to 0—Modes 3 to 0 (MD3 to MD0): These bits are used to set the timer operating mode.
Bit 3 Bit 2 Bit 1
* 2
*1
MD3 MD2 MD1
0 0 0
1
1 0
1
1 * *
Notes: *1 MD3 is a reserved bit. In a write, it should always be written with 0.
*2 Phase counting mode cannot be set for channels 0 and 3. In this case, 0 should always
be written to MD2.
310
Bit 0
MD0 Description
0 Normal operation
1 Reserved
0 PWM mode 1
1 PWM mode 2
0 Phase counting mode 1
1 Phase counting mode 2
0 Phase counting mode 3
1 Phase counting mode 4
* —
(Initial value)
(Initial value)
*: Don't care