Special Status Word Format - Motorola MC68020 User Manual

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FC FB RC
FC—Fault on Stage C
When the FC bit is set, the processor attempted to use stage C and found it to be
marked invalid due to a bus error on the prefetch for that stage. FC can be used by a
bus error handler to determine the cause(s) of a bus error exception.
FB—Fault on Stage B
When the FB bit is set, the processor attempted to use stage B and found it to be
marked invalid due to a bus error on the prefetch for that stage. FB can be used by a
bus error handler to determine the cause(s) of a bus error exception.
RC—Rerun Flag for Stage C
The RC bit is set to indicate that a fault occurred during a prefetch for stage C. The RC
bit is always set when the FC bit is set. The RC bit indicates that the word in stage C of
the instruction pipe is invalid, and the state of the bit can be used by a handler to repair
the values in the pipe after an address error or a bus error, if necessary. If the RC bit is
set when the processor executes an RTE instruction, the processor may execute a bus
cycle to prefetch the instruction word for stage C of the pipe (if it is required). If the RC
and FC bits are set, the RTE instruction automatically reruns the prefetch cycle for
stage C. The address space for the bus cycle is the program space for the privilege
level indicated in the copy of the SR on the stack. If the RC bit is clear, the words on the
stack for stage C of the pipe are accepted as valid; the processor assumes that there is
no prefetch pending for stage C and that software has repaired or filled the image of
stage C, if necessary.
1 = Rerun faulted bus cycle or run pending prefetch
0 = Do not rerun bus cycle
RB—Rerun Flag for Stage B
The RB bit is set to indicate that a fault occurred during a prefetch for stage B. The RB
bit is always set when the FB bit is set. The RB bit indicates that the word in stage B of
the instruction pipe is invalid, and the state of the bit can be used by a handler to repair
the values in the pipe after an address error or a bus error, if necessary. If the RB bit is
set when the processor executes an RTE instruction, the processor may execute a bus
cycle to prefetch the instruction word for stage B of the pipe (if it is required). If the RB
and FB bits are set, the RTE instruction automatically reruns the prefetch cycle for stage
B. The address space for the bus cycle is the program space for the privilege level
indicated in the copy of the SR on the stack. If the RB bit is clear, the words on the
MOTOROLA
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RB 0 0 0 DF
Figure 6-8. Special Status Word Format
M68020 USER'S MANUAL
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RM RW SIZE
3 2 0
0 FC2–FC0
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