Fujitsu MB91460 SERIES FR60 User Manual page 443

The selection of the appropriate BADx register (point 0 or 2) for the mask value depends on EP0 and ER0. If at least
one of both bits are enabled, the mask usage switches to point 2 due to the allocation of point 0. Otherwise the
default mask stored in point 0 applies for CMP0. If MPE=1 and COMB=1 the mask is taken from point 0, regardless
of the setting of EP0 and ER0.
BIT[1]: ER1 - Enable Range for CMP1
0 Range detection CMP1 (channels 2-3) is disabled (default)
1 Range detection CMP1 (channels 2-3) is enabled
If ER1 is enabled then the registers BADx, point 3 and point 2 will be used for range comparison:
Point 2 <= Compare Value <= Point 3.
If a mask is set with EM1 then both point registers will be masked with the mask register content.
Point 3 and Point 2 are taken from BAD[x+3] and BAD[x+2], the mask is stored in Point 0, BAD[x+0].
The 'x' is the group offset and calculates by the group index multiplied with 4.
BIT[0]: ER0 - Enable Range for CMP0
0 Range detection CMP0 (channels 0-1) is disabled (default)
1 Range detection CMP0 (channels 0-1) is enabled
If ER0 is enabled then the registers BADx, point 1 and point 0 will be used for range comparison:
Point 0 <= Compare Value <= Point 1.
If a mask is set with EM0 then both point registers will be masked with the mask register content.
In the special case of MPE=1 together with COMB=1, Point 1 and Point 0 are taken from the opposite channel
BAD[x+3] and BAD[x+2] and the mask is stored in Point 0, BAD[x+0]. Otherwise Point 1 and Point 0 are taken from
BAD[x+1] and BAD[x+0], the mask is stored in Point 2, BAD[x+2].
The 'x' is the group offset and calculates by the group index multiplied with 4.
● Break Address/Data register (BAD0...BAD31)
The BADx registers define 32 break point addresses, data values or mask information for the 8 groups of channels.
For each group of channels there are 4 dedicated BAD registers. BAD0, BAD1, BAD2 and BAD3 belong to Group
0, BAD4, BAD5, BAD6 and BAD7 belong to Group 1 and so on. The functionality described below for the registers
of group 0 is representative for all the other groups too. The index of the BADx registers has to be incremented by
4 for each of the next group indexes.
Address
F080 XXXXXXXX
H
This register sets the 32 bit comparison value for break point 0 of CMP0. In range mode (set with ER0) the register
value of BAD0 functions as lower address limit. In addition BAD0 could be used as mask register.
In the special case of MPE=1 and COMB=1 BAD0 is not used for the point definition. CMP0 gets its point configu-
ration then from BAD2.
BAD0 (BAD4, BAD8, ..., BAD28) [R/W]
+0 +1
XXXXXXXX
+2
XXXXXXXX XXXXXXXX
Chapter 29 MPU / EDSU
4.Registers
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