Fujitsu MB91460 SERIES FR60 User Manual page 332

32-bit microcontroller
Table of Contents

Advertisement

Chapter 24 Interrupt Control
4.Registers
ICR (Interrupt Control Register) is a register in the interrupt controller, and it specifies the interrupt level for
each interrupt request. ICR corresponds to each of interrupt request input. ICR is mapped to the I/O space.
• ICR00 – ICR63
7
6
RX/WX
RX/WX
(About attributes, see
• Bit 7-5: Undefined. Writing does not affect the operation. The read value is indeterminate.
• Bit 4-0: Interrupt level setting bits
ICR4-ICR0 bits
0000-01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
• The interrupt level setting bit specifies the interrupt level of the corresponding interrupt request.
• When the interrupt level set to the interrupt control register is the same as, or higher than the level mask
value set to the ILM register of the CPU, the interrupt request is masked by the CPU side.
316
5
4
ICR4
1
RX/WX
R/WX
"Meaning of Bit Attribute Symbols (Page
Interrupt level
0-14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
3
2
ICR3
ICR2
ICR1
1
1
R/W
R/W
R/W
No.10)".)
Description
Reserved for system (cannot to be set)
The highest level
(High)
(Low)
The lowest level
Disable interrupts
1
0
bit
ICR0
Initial
1
1
value
R/W
Attribute
NMI

Advertisement

Table of Contents
loading

This manual is also suitable for:

Fr60Mb91460 series

Table of Contents