Fujitsu MB91460 SERIES FR60 User Manual page 652

Chapter 32 USART (LIN / FIFO)
4.USART Registers
4.9 FIFO Status Register (FSR04)
7
R
:
R :
:
(Note) The FSR04[4:0] FIFO valid data bits indicates the number of stored receptions (SVD=0) or pending
transmissions (SVD=1) in the FIFO buffer.
636
Figure 4-9 Configuration of FIFO status register
6 5 4 3 2 1
R R R R R R
Flag is read only, writing to it
has no effect
Initial value
Initial value
0
0 0 0 0 0 0 0 0
B
R
bit 0
0 FIFO: number of valid Data Bit 0
bit 1
0 FIFO: number of valid Data Bit 1
bit 2
0 FIFO: number of valid Data Bit 2
bit 3
0 FIFO: number of valid Data Bit 3
bit 4
FIFO: number of valid Data Bit 4
0
bit 5
not used / always read 0
bit 6
not used / always read 0
bit 7
not used / always read 0
FIFO valid data number
FIFO valid data number
FIFO valid data number
FIFO valid data number
FIFO valid data number